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专利名称：Background comparator offset calibration
technique for flash analog-to-digitalconverters
发明人：Chun-Cheng Huang,Jieh-Tsorng Wu申请号：US11135218申请日：20050523公开号：US070693B1公开日：20060620
专利附图：
摘要：A background-calibrated comparator and a background-calibrated flashanalog-to-digital converter are disclosed for using in mixed-signal integrated circuit
design in particular on the high-speed analog-to-digital converter circuit. Withoutaffecting the operation of the comparator, the disclosure is directed at reducing theunpredictable input offset voltage originated from the variation of process parametersand environmental factors. The background-calibrated comparator includes a randomchopping comparator, a calibration processor, and a random sequence generator. Thebackground-calibrated flash analog-to-digital converter (ADC) includes a background-calibrated comparator array together with a reference voltage generator, athermometer code edge detector, and a set of digital encoders.
申请人：Chun-Cheng Huang,Jieh-Tsorng Wu
地址：Hsinchu TW,Hsin-chu TW
国籍：TW,TW
代理机构：Bucknam and Archer
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