ucc22

UCC21, UCC22UCC23, UCC24ąSLUS542F − OCTOBER 2003 − REVISED JULY 2009CURRENTĆMODEACTIVE CLAMP PWM CONTROLLERFEATURESDLow Output JitterDSoft−Stop Shutdown of MAIN and AUXDIdeal for Active Clamp/Reset Forward,DDDDDDDDDDESCRIPTIONThe UCC21/2/3/4 family of PWM controllers isdesigned to simplify implementation of the variousactive clamp/reset switching power topologies.The UCC2x is a peak current-mode, fixed-frequency, high-performance pulse width modulator.It includes the logic and the drive capability for theauxiliary switch with a simple method ofprogramming the critical delays for proper activeclamp operation.The UCC21/3 includes a 110-V start-upregulator for initial start-up and to providekeep-alive power during stand-by.Additional features include an internalprogrammable slope compensation circuit,precise DMAX limit, and a single resistorprogrammable synchronizable oscillator. Anaccurate line monitoring function also programsthe converter’s ON and OFF transitions withregard to the bulk input voltage. Along with theUCC27, this UCC2x family allows the powersupply designer to eliminate many of the externalcomponents, reducing the size and complexity ofthe design.Flyback ConvertersProvides Complementary Auxiliary Driverwith Programmable Deadtime (Turn-OnDelay) between AUX and MAIN SwitchesPeak Current-Mode Control withCycle-by-Cycle Current Limiting110-V Input Startup Regulator on UCC21/3TrueDrivet 2-A Sink, 2-A Source OutputsAccurate Line UV and Line OV ThresholdProgrammable Slope Compensation1.0-MHz Synchronizable OscillatorPrecise Programmable Maximum Duty CycleProgrammable Soft Start APPLICATIONSD150-W to 700-W SMPSDHigh-Efficiency, Low EMI/RFI Off-Line orDDDC/DC ConvertersServer, 48-V Telecom, DatacomHigh Power Adapter, LCD-TV and PDP-TVRDEL1RONROFF234CVREF56CF78RSLOPEUCC21VINRDELRTONRTOFFVREFSYNCGNDCSRSLOPELINE UVVDDOUTBIASWINDING16CBULK1514131211109RFCSSDAUXCBIASROUTCAUXCCLAMP+VIND3Q1D1Q3Q4D4LoCoLOADQ2D2RCSSRDRIVEAUXPGNDSS/SDFBSECONDARYSIDE E/APlease be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.Copyright  2003 − 2009, Texas Instruments Incorporatedwww.ti.com1SLUS542F − OCTOBER 2003 − REVISED JULY 2009UCC21, UCC22UCC23, UCC24ąThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.ABSOLUTE MAXIMUM RATINGSover operating free-air temperature range unless otherwise noted(1)UNITLine input voltage, VINSupply voltage, VDDAnalog inputsOutput source current (peak), IO_SOURCEOutput sink current (peak), IO_SINKOperating junction temperature range, TJStorage temperature, TstgESD ratingHuman body model, (HBM)Change device model (CDM)120(IDD < 10 mA)FB, CS, SYNC, LINEOV, LINEUVOUT, AUX16.5−0.3 to (VREF + 0.3)not to exceed 62.5−2.5−55 to 150−65 to 1502000500VVVA°CVLead temperature, Tsol, 1,6 mm (1/16 inch) from case for 10 seconds300°C(1)Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” isnot implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect toGND. Currents are positive into and negative out of, the specified terminal.RECOMMENDED OPERATING CONDITIONSMINLine input voltage, VINSupply voltage, VDDSupply bypass capacitanceTiming resistance, RON = ROFF (for 250-kHzoperation)Operating junction temperature, TJReference bypass capacitance, CREF−400.1188.5175105112.0NOMMAX11016.0UNITVVµFkΩ°CµFORDERING INFORMATIONPART NUMBERSAUXOUTPUTPOLARITYCSTHRESHOLD(INCLUDESSLOPE COM-PENSATION)0.75 V1.27 V0.75 V1.27 V110-V START-UPCIRCUITSOIC−16(D)TSSOP−16(PW)TAAPPLICATIONDC−DC−40°C to 125°CDC-DC/Sec. SideDC−DCOff−LineP-ChannelN-ChannelYesNoYesNoUCC21DUCC22DUCC23DUCC24DUCC21PWUCC22PWUCC23PWUCC24PW†The D and PW packages are available taped and reeled. Add R suffix to device type (e.g. UCC21DR) to order quantities of 2,500devices per reel (for the D package) and 2,000 devices per reel (for the PW package). Bulk quantities are 40 units per tube (for the Dpackage) and 90 units per tube (for the PW package).2www.ti.comSLUS542F − OCTOBER 2003 − REVISED JULY 2009UCC21, UCC22UCC23, UCC24ąTHERMAL RESISTANCE INFORMATIONPACKAGESOIC−16 (D)TSSOP−16 (PW)θjcθja (0 LFM)θjcθja (0 LFM)THERMAL RESISTANCE36.9 to 38.473.1 to 111.633.6 to 35.0108.4 to 147.0UNITS°C/W°C/WPIN ASSIGNMENTSUCC21 AND UCC23D and PW PACKAGEs(TOP VIEW)UCC22 AND UCC24D AND PW PACKAGE(TOP VIEW)RTDELRTONRTOFFVREFSYNCGNDCSRSLOPE1234 5678161514131211109VINLINEUVVDDOUTAUXPGNDSS/SDFBRTDELRTONRTOFFVREFSYNCGNDCSRSLOPE1234 5678161514131211109LINEOVLINEUVVDDOUTAUXPGNDSS/SDFBVDD = 12 V(1), 1-µF capacitor from VDD to GND, 0.01-µF capacitor from VREF to GND, RON = ROFF = 75 kΩ, RDEL = 10 kΩ,RSLOPE = 50 kΩ, −40 °C ≤ TA = TJ ≤125°C (unless otherwise noted)PARAMETERTEST CONDITIONSMINTYPMAXOVERALLISTARTUPIDDStart-up currentOperating supply current(1)(2)VDD < VUVLOVFB = 0 V, VCS = 0 V,Outputs not switchingCurrent available from VDD during Start-up, VIN = 36 V, TA = −40°C to 85°C (3)VIN = 120 V; VDD = 14 V12.27..41.24311.8RTON = 75 kΩRTON = 75 kΩ−10.510.512.78.04.71.26812.530025003ELECTRICAL CHARACTERISTICS UNITµAmAHIGH-VOLTAGE BIAS SECTION (UCC21, UCC23)IDD−STVDD startup current4117513.28.45.01.29314.5−18.518.5VµAVmAµAIVINJFET leakage currentUNDERVOLTAGE LOCKOUTStart threshold voltage(1)Minimum operating voltage after startHysteresisLINE MONITORVLINEUVILINEHYSISSISSLine UV and Line OV voltage thresholdLine UV and Line OV hysteresis currentCharge currentDischarge currentSOFT-STARTµAVSS/SDDischarge/shutdown threshold voltage0.40.50.6V(1)Set VDD above the start threshold before setting at 12 V.(2)Does not include current of the external oscillator network.(3)The power supply starts with IDD−ST load on VDD, part will start up with no load up to 125°C. For more detailed information, see pin descriptionsfor VIN and VDD.(4)ISSC and ISS/SD are directly proportional to IRON. See equation 7.www.ti.com3SLUS542F − OCTOBER 2003 − REVISED JULY 2009UCC21, UCC22UCC23, UCC24ąVDD = 12 V(1), 1-µF capacitor from VDD to GND, 0.01-µF capacitor from VREF to GND, RON = ROFF = 75 kΩ, RDEL = 10 kΩ,RSLOPE = 50 kΩ, −40 °C ≤ TA = TJ ≤125°C (unless otherwise noted)PARAMETERTEST CONDITIONSMINTYPMAXVoltage ReferenceVREFReference voltageTJ = 25°C0 A < IREF < 5 mA, over temperatureREF = 0 V, TJ = 25°C4.854.75−205.005.00−115.155.25−8ELECTRICAL CHARACTERISTICS UNITVmAISCShort circuit currentINTERNAL SLOPE COMPENSATIONmSlope(3)FB = High-10%RCSRSLOPE2502+10%OSCILLATORfOSCOscillator frequencyTotal variationVP_POscillator amplitude (peak-to-peak)SYNCHRONIZATIONVSYNCHtDELPWMMaximum duty cycleMinimum duty cyclePWM offsetCURRENT SENSEVLVLVERR(max)VCSVCSCurrent sense level shift voltageMaximum voltage error (clamped)Current sense thresholdCurrent sense thresholdUCC21UCC23UCC22UCC240.404.80.711.230.505.00.751.270.605.20.791.31VCS = 0 V0.430.5066%70%74%0%0.61VSYNC theshold voltageSYNC-to-output delay1.6TJ = 25°C−40 °C < TJ 125°C; 8.5 V < 14.5 V237225263270kHzV3.0Vns2.350(1)Set VDD above the start threshold before setting at 12 V.(2)Does not include current of the external oscillator network.4www.ti.comSLUS542F − OCTOBER 2003 − REVISED JULY 2009UCC21, UCC22UCC23, UCC24ąVDD = 12 V(1), 1-µF capacitor from VDD to GND, 0.01-µF capacitor from VREF to GND, RON = ROFF = 75 kΩ, RDEL = 10 kΩ,RSLOPE = 50 kΩ, −40 °C ≤ TA = TJ ≤125°C (unless otherwise noted)PARAMETERTEST CONDITIONSMINTYPMAXOUTPUT (OUT AND AUX)tRtFtDEL1tDEL2IOUT(src)IOUT(sink)VOUT(low)VOUT(high)Rise timeFall timeDelay time (AUX to OUT)Delay time (OUT to AUX)Output source currentOutput sink currentLow-level output voltageHigh-level output voltageIOUT = 150 mAIOUT = −150 mACLOAD = 2 nFCLOAD = 2 nFCLOAD = 2 nF, CLOAD = 2 nF, RDEL = 10 kΩRDEL = 10 kΩ1914110115−220.411.12823ELECTRICAL CHARACTERISTICS UNITnsAV50%OUT50%tAUX50%50%(N−channel)tAUX50%50%(P−channel)ttDEL1tDEL2Figure 1. Output Timing Diagramwww.ti.com5SLUS542F − OCTOBER 2003 − REVISED JULY 2009UCC21, UCC22UCC23, UCC24ąFUNCTIONAL BLOCK DIAGRAMTYP: VREF = 5.0 VVREF0.05 * IRDEL1/2 x VREFIRDELRDEL11/2 x VREFCLOCKUV+1.27 V13 V/ 8 VRTON21/2 x VREFIRTONRTOFF3VDDCTSYNC1−DMAXOUTPWMOFFVREFIRDELOUTPWM Offset0.5 V++R75kVREF5 * ISLOPEGNDCS671−DMAX+OV OFFVREFUV OFFUCC22/4UCC21/3CTISLOPERSLOPE81.27 V0.75 V2 * R3 * RISS = 0.43 x IRTON+VDDUVVREFOV+UVLOANDSS10SS/SDTURN−ONDELAY93/94N−Ch.QVREFIRDEL91/92P−Ch.VDDAUXSQTURN−ONDELAYVDDVDD14VDD+VDDOKVREF0.05 * IRDEL+1.27 V91/9315LINEUV92/9416VIN (UCC21/3)LINEOV (UCC22/4)OVVREF4REFGEN13OUTSYNC51211PGNDENABLE9FB6www.ti.comSLUS542F − OCTOBER 2003 − REVISED JULY 2009UCC21, UCC22UCC23, UCC24ąTERMINAL FUNCTIONSTERMINALNAMEAUXUCC21UCC2312UCC22UCC2412I/ODESCRIPTIONThis output drives the auxiliary clamp MOSFET which is turned on when the main PWMswitching device is turned off. The AUX pin can directly drive the auxiliary switch with 2-Asource turn-on current and 2-A sink turn-off current.This pin is used to sense the peak current utilized for current mode control and for currentlimiting functions. The peak signal which can be applied to this pin before pulse-by-pulsecurrent limiting activates is approximately 0.75 V for the UCC21 and UCC23 and 1.27 Vfor the UCC22 and UCC24.This pin is used to bring the error signal from an external optocoupler or error amplifier intothe PWM control circuitry. Often, there is a resistor tied from FB to VREF, and an optocoup-ler is used to pull the control pin closer to GND to reduce the pulse width of the OUT outputdriving the main power switch of the converter.This pin serves as the fundamental analog ground for the PWM control circuitry. This pinshould be connected to PGND directly at the device.For the UCC22/4, provides the LINE overvoltage function.This pin provides a means to accurately enable/disable the power converter stage by moni-toring the bulk input voltage or another parameter. When the circuit initially starts (or restartsfrom a disabled condition), a rising input on LINEUV enables the outputs when the thresholdof 1.27 V is crossed. After the circuit is enabled, then a falling LINEUV signal disables theoutputs when the same threshold is reached. The hysteresis between the two levels is pro-grammed using an internal current source.This output pin drives the main PWM switching element MOSFET in an active clamp control-ler. It can directly drive an N-channel device with 2-A source turn-on current and 2-A sinkturn-off current. A 10−kΩ resistor is recommended to connect this pin to PGND.The PGND should serve as the current return for the high-current output drivers OUT andAUX. Ideally, the current path from the outputs to the switching devices, and back would beas short as possible, and enclose a minimal loop area.A resistor connected from this pin to GND programs an internal current source that sets theslope compensation ramp for the current mode control circuitry.A resistor from this pin to GND programs the turn-on delay of the two gate drive outputs toaccommodate the resonant transitions of the active clamp power converter.A resistor connected from this pin to GND programs an internal current source that dis-charges the internal timing capacitor.A resistor connected from this pin to GND programs an internal current source that chargesthe internal timing capacitor.A capacitor from SS/SD to ground is charged by an internal current source of IRTON to pro-gram the soft-start interval for the controller. During a fault condition this capacitor is dis-charged by a current source equal to IRTON.The SYNC pin serves as a unidirectional synchronization input for the internal oscillator. Thesynchronization function is implemented such that the user programmable maximum dutycycle (set by RTON and RTOFF) remains accurate during synchronized operation.This is the power supply for the device. There should be a 1-µF capacitor directly from VDDto PGND. The capacitor value should be minimum 10 times greater than that on VREF.PGND and GND should be connected externally and directly from PGND to GND.For the UCC21 and UCC23, this pin is connected to the input power rail directly. Insidethe device, a high-voltage start-up device is utilized to provide the start-up current for thecontroller until a bootstrap type bias rail becomes available.This is the 5-V reference voltage that can be utilized for an external load of up to 5 mA.Since this reference provides the supply rail for internal logic, it should be bypassed toAGND as close as possible to the device. The VREF bias profile may not be monotonicbefore VDD reached 5 V.OCS77IFB99IGNDLINEOV6−616−ILINEUV1515IOUT1313OPGNDRSLOPERTDELRTOFFRTONSS/SD1181321011813210−IIIIISYNC55IVDD1414IVIN16−IVREF44Owww.ti.com7SLUS542F − OCTOBER 2003 − REVISED JULY 2009UCC21, UCC22UCC23, UCC24ąDETAILED PIN DESCRIPTIONSRDEL (pin 1)This pin is internally connected to an approximately 2.5-V DC source. A resistor (RDEL) to GND (pin 6) sets theturn-on delay for both gate drive signals of the UCC2981 family of controllers. The delay time is identical for bothswitching transitions, between OUT (pin 13) is turning off and AUX (pin 14) is turning on as well as when AUX(pin 14) is turning off and OUT (pin 13) is turning on. The delay time is defined as:tDEL1+tDEL2+11.1 10*12 RDEL)15 10*9seconds(1)For proper selection of the delay time refer to the various references describing the design of active clamp powerconverters.RTON (pin 2)This pin is internally connected to an approximately 2.5-V DC source. A resistor (RON) to GND (pin 6) sets thecharge current of the internal timing capacitor. The RTON pin, in conjunction with the RTOFF pin (pin 3) are usedto set the operating frequency and maximum operating duty cycle of the UCC21 family.RTOFF (pin3)This pin is internally connected to an approximately 2.5-V DC source. A resistor (ROFF) to GND (pin 6) sets thedischarge current of the internal timing capacitor. The RTON and RTOFF pins are used to set the switchingperiod (TSW) and maximum operating duty cycle (DMAX) according to the following equations:tON+36.1 10*12 RON*tDEL1secondstOFF+15 10*12 ROFF)tDEL1)170 10*9secondsTSW+tON)tOFFDMAX+tONTSW(2)(3)(4)(5)VREF (pin 4)The controller’s internal, 5-V bias rail is connected to this pin. The internal bias regulator requires a good qualityceramic bypass capacitor (CVREF) to GND (pin 6) for noise filtering and to provide compensation to the regulatorcircuitry. The recommended CVREF value is 0.22-µF. The minimum bypass capacitor value is 0.022-µF limitedby stability considerations of the bias regulator, while the maximum is approximately 22-µF. Also, capacitorvalue on VDD should be minimum 10 times greater than that on VREF.The VREF pin is internally current limited and can supply approximately 5-mA to external circuits. The 5-V biasis only available when the undervoltage lock out (UVLO) circuit enables the operation of UCC2x controllers.For the detailed functional description of the undervoltage lock out (UVLO) circuit refer to the FunctionalDescription section of this datasheet.8www.ti.comSLUS542F − OCTOBER 2003 − REVISED JULY 2009UCC21, UCC22UCC23, UCC24ąDETAILED PIN DESCRIPTIONS (continued)SYNC (pin 5)This pin provides an input for an external clock signal which can be used to synchronize the internal oscillatorof the UCC2x family of controllers. The synchronizing frequency must be higher than the free runningfrequency of the onboard oscillator ǒTSYNCtTSWǓ. The acceptable minimum pulse width of thesynchronization signal is approximately 50 ns (positive logic), and it should remain shorter thanǒ1*DMAXǓ TSYNC where DMAX is set by RON and ROFF. If the pulse width of the synchronization signal stayswithin these limits, the maximum operating duty ratio remains valid as defined by the ratio of RON and ROFF,and DMAX is the same in free running and in synchronized modes of operation. If the pulse width of thesynchronization signal would exceed the ǒ1*DMAXǓ TSYNC limit, the maximum operating duty cycle isdefined by the synchronization pulse width.For more information on synchronization of the UCC21 family refer to the Functional Description section ofthis datasheet.GND (pin 6)This pin provides a reference potential for all small signal control and programming circuitry inside the UCC21family.CS (pin 7)This is a direct input to the PWM and current limit comparators of the UCC21 family of controllers. The CSpin should never be connected directly across the current sense resistor (RCS) of the power converter. A small,customary R−C filter between the current sense resistor and the CS pin is necessary to accommodate theproper operation of the onboard slope compensation circuit and in order to protect the internal dischargetransistor connected to the CS pin (RF, CF).Slope compensation is achieved across RF by a linearly increasing current flowing out of the CS pin. The slopecompensation current is only present during the on-time of the gate drive signal of the main power switch (OUT)of the converter. The internal pull-down transistor of the CS pin is activated during the discharge time of thetiming capacitor. This time interval is ǒ1*DMAXǓ TSW long and represents the guaranteed off time of themain power switch.RSLOPE (pin 8)A resistor (RSLOPE) connected between this pin and GND (pin 6) sets the amplitude of the slope compensationcurrent. During the on time of the main gate drive output (OUT) the voltage across RSLOPE is a representationof the internal timing capacitor waveform. As the timing capacitor is being charged, the voltage across RSLOPEalso increases, generating a linearly increasing current waveform. The current provided at the CS pin for slopecompensation is proportional to this current flowing through RSLOPE.Due to the high speed, AC voltage waveform present at the RSLOPE pin, the parasitic capacitance andinductance of the external circuit components connected to the RSLOPE pin should be carefully minimized.For more information on how to program the internal slope compensation refer to the Setup Guide section ofthis datasheet.www.ti.com9SLUS542F − OCTOBER 2003 − REVISED JULY 2009UCC21, UCC22UCC23, UCC24ąDETAILED PIN DESCRIPTIONS (continued)FB (pin 9)This pin is an input for the control voltage of the pulse width modulator of the UCC21 family. The controlvoltage is generated by an external error amplifier by comparing the converters output voltage to a voltagereference and employing the compensation for the voltage regulation loop. Usually, the error amplifier is locatedon the secondary side of the isolated power converter and its output voltage is sent across the isolationboundary by an opto coupler. Thus, the FB pin is usually driven by the opto coupler. An external pull-up resistorto the VREF pin (pin 4) is also needed for proper operation as part of the feedback circuitry.The control voltage is internally buffered and connected to the PWM comparator through a voltage divider tomake it compatible to the signal level of the current sense circuit. The useful voltage range of the FB pin isbetween approximately 1.25 V and 4.5 V. Control voltages below the 1.25-V threshold result in zero duty cycle(pulse skipping) while voltages above 4.5 V result in full duty cycle (DMAX) operation.SS/SD (pin 10)A capacitor (CSS) connected between this pin and GND (pin 6) programs the soft start time of the powerconverter. The soft-start capacitor is charged by a precise, internal DC current source which is programmed bythe RON resistor connected to pin 2. The soft-start current is defined as:ISS+0.43 IRTON+0.43 VREF 12RON(6)This DC current charges CSS from 0 V to approximately 5 V. Internal to the UCC21 family of controllers, thesoft start capacitor voltage is buffered and ORed with the control voltage present at the FB pin (pin 9). The lowerof the two voltages manipulates the controller’s PWM engine through the voltage divider described with regardsto the FB pin. Accordingly, the useful control range on the SS pin is similar to the control range of the FB pinand it is between 1.25 V and 4.5 V approximately.PGND (pin 11)This pin serves as a dedicated connection to all high-current circuits inside the UCC21 family of parts. Thehigh-current portion of the controller consists of the two high-current gate drivers, and the various biasconnections except VREF (pin 4). The PGND (pin 11) and GND (pin 6) pins are not connected internally, alow-impedance, external connection between the two ground pins is also required. It is recommended to forma separate ground plane for the low current setup components (RDEL, RON, ROFF, CVREF, CF, RSLOPE, CSS andthe emitter of the opto-coupler in the feedback circuit). This separate ground plane (GND) should have a singleconnection to the rest of the ground of the power converter (PGND) and this connection should be between pin6 and pin 11 of the controller.AUX (pin 12)This is a high-current gate drive output for the auxiliary switch to implement the active clamp operation for thepower stage. The auxiliary output (AUX) of the UCC21 and UCC22 drives a P-channel device as the clampswitch therefore it requires an active low operation (the switch is ON when the output is low). The UCC23and UCC24 controllers are optimized for N-channel auxiliary switch therefore it employs the traditional activehigh drive signal.10www.ti.comSLUS542F − OCTOBER 2003 − REVISED JULY 2009UCC21, UCC22UCC23, UCC24ąDETAILED PIN DESCRIPTIONS (continued)OUT (pin 13)This high-current output drives an external N-channel MOSFET. Each controller in the UCC21 family usesactive high drive signals for the main switch of the converter.Due to the high speed and high-drive current capability of these outputs (AUX, OUT) the parasitic inductanceof the external circuit components connected to these pins should be carefully minimized. A potential way ofavoiding unnecessary parasitic inductances in the gate drive circuit is to place the controller in close proximityto the MOSFETs and by ensuring that the outputs (AUX, OUT) and the gates of the MOSFET devices areconnected by wide, overlapping traces.VDD (pin 14)The VDD rail is the primary bias for the internal, high-current gate drivers, the internal 5-V bias regulator andfor parts of the undervoltage lockout circuit. To reduce switching noise on the bias rail, a good quality ceramiccapacitor (CHF) must be placed very closely between the VDD pin and PGND (pin 11) to provide adequatefiltering. The recommended CHF value is 1-µF for most applications but its value might be affected by theproperties of the external MOSFET transistors used in the power stage.In addition to the low-impedance, high-frequency filtering, the controller’s bias rail requires a larger value energystorage capacitor (CBIAS) connected parallel to CHF. The energy storage capacitor must provide the hold up timeto operate the UCC21 family (including gate drive power requirements) during start up. In steady stateoperation the controller must be powered from a bootstrap winding off the power transformer or by an auxiliarybias supply. In case of an independent auxiliary bias supply, the energy storage is provided by the outputcapacitance of the bias supply. When using the internal JFET for startup, the external load on VDD must belimited to less than 4 mA.LINEUV (pin 15)This input monitors the incoming power source to provide an accurate undervoltage lockout function with userprogrammable hysteresis for the power supply controlled by the UCC21 family. The unique property of theUCC21 family is to use only one pin to implement these functions without sacrificing on performance. Theinput voltage of the power supply is scaled to the precise 1.27-V threshold of the undervoltage lockoutcomparator by an external resistor divider (RIN1, RIN2 in Figure 7). Once the line monitor’s input threshold isexceeded, an internal current source gets connected to the LINEUV pin. The current generator is programmedby the RDEL resistor connected to pin 1 of the controller. The actual current level is given as:IHYST+VREF 1 0.052RDEL(7)As this current flows through RIN2 of the input divider, the undervoltage lockout hysteresis is a function of IHYSTand RIN2 allowing accurate programming of the hysteresis of the line monitoring circuit.For more information on how to program the line monitoring function refer to the Setup Guide of this datasheet.www.ti.com11SLUS542F − OCTOBER 2003 − REVISED JULY 2009UCC21, UCC22UCC23, UCC24ąDETAILED PIN DESCRIPTIONS (continued)VIN (pin 16 − UCC21 and UCC23 only)The UCC21 and UCC23 controllers are equipped with a high voltage, P-channel JFET start up device toinitiate operation from the input power source of the converter in applications where the input voltage does notexceed the 110-V maximum rating of the start up transistor. In these applications, the VIN pin can be connecteddirectly to the positive terminal of the input power source. The internal JFET start up transistor providesapproximately 15-mA charge current for the energy storage capacitor (CBIAS) connected across the VDD (pin14) and PGND (pin 11) terminals. Note that the start up device is turned off immediately when the voltage onthe VDD pin exceeds approximately 13.5 V, the controller’s undervoltage lockout threshold for turn-on. TheJFET is also disabled at all times when the high-current gate drivers are switching to protect against excessivepower dissipation and current through the device. When using the internal JFET for startup, the external loadon VDD must be limited to less than 4 mA.For more information on biasing the UCC21 family, refer to the Setup Guide and Additional ApplicationInformation Sections of this datasheet.LINEOV (pin 16 − UCC22 and UCC24 only)In the UCC22 and UCC24 controllers the high-voltage start-up device is not utilized thus pin 16 is usedfor a different function. This input monitors the incoming power source to provide an accurate overvoltageprotection with user programmable hysteresis for the power supply controlled by the controller. The circuitimplementation of the overvoltage protection function is identical to the technique used for monitoring the inputpower rail for undervoltage lockout. This allows implementing an accurate threshold and hysteresis using onlyone pin. The input voltage of the power supply is scaled to the precise 1.27-V threshold of the overvoltageprotection comparator by an external resistor divider (RIN3, RIN4 in Figure 7). Once the line monitor’s inputthreshold is exceeded, an internal current source gets connected to the LINEOV pin. The current generator isprogrammed by the RDEL resistor connected to pin 1 of the controller. The actual current level is given as:IHYST+VREF 1 0.052RDEL(8)As this current flows through RIN4 of the input divider, the overvoltage protection hysteresis is a function of IHYSTand RIN4 allowing accurate programming of the hysteresis of the line monitoring circuit.For more information on how to program the overvoltage protection, refer to the Setup Guide of this datasheet.12www.ti.comSLUS542F − OCTOBER 2003 − REVISED JULY 2009UCC21, UCC22UCC23, UCC24ąFUNCTIONAL DESCRIPTIONJFET Control and UVLOThe UCC21 and UCC23 controllers include a high voltage JFET start up transistor. The steady state powerconsumption of the of the control circuit which also includes the gate drive power loss of the two power switchesof an active clamp converter exceeds the current and thermal capabilities of the device. Thus the JFET shouldonly be used for initial start up of the control circuitry and to provide keep-alive power during stand-by modewhen the gate drive outputs are not switching. Accordingly, the start-up device is managed by its own controlalgorithm implemented on board the UCC21 and UCC23. The following timing diagram illustrates theoperation of the JFET start up device.VONVIN13.5V10.0VVDDBootstrap bias8V 4.5V)the voltage on the CS pin is below the current limit thresholdthe control voltage is above the zero duty cycle boundary (VFB > 1.25 V)the input voltage is in the valid operating range (VVONwww.ti.com

5-Mar-2011

PACKAGING INFORMATION

Orderable Device

UCC21DUCC21DG4UCC21DRUCC21DRG4UCC21PWUCC21PWG4UCC21PWRUCC21PWRG4UCC22DUCC22DG4UCC22DRUCC22DRG4UCC22PWUCC22PWG4UCC22PWRUCC22PWRG4UCC23D

Status

(1)

Package TypePackage

Drawing

SOICSOICSOICSOICTSSOPTSSOPTSSOPTSSOPSOICSOICSOICSOICTSSOPTSSOPTSSOPTSSOPSOIC

DDDDPWPWPWPWDDDDPWPWPWPWD

Pins1616161616161616161616161616161616

Package Qty

40402500250090902000200040402500250090902000200040

Eco Plan

(2)

Lead/Ball Finish

MSL Peak Temp

(3)

Samples(Requires Login)

ACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVE

Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)

CU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIM

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

5-Mar-2011

Orderable DeviceUCC23DG4UCC23DRUCC23DRG4UCC23PWUCC23PWG4UCC23PWRUCC23PWRG4UCC24DUCC24DG4UCC24DRUCC24DRG4UCC24PWUCC24PWG4UCC24PWRUCC24PWRG4

(1)

Status

(1)

Package TypePackage

Drawing

SOICSOICSOICTSSOPTSSOPTSSOPTSSOPSOICSOICSOICSOICTSSOPTSSOPTSSOPTSSOP

DDDPWPWPWPWDDDDPWPWPWPW

Pins161616161616161616161616161616

Package Qty

4025002500909020002000404025002500909020002000

Eco Plan

(2)

Lead/Ball Finish

MSL Peak Temp

(3)

Samples(Requires Login)

ACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVE

Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)

CU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIM

The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

5-Mar-2011

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms \"Lead-Free\" or \"Pb-Free\" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines \"Green\" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3

PACKAGEMATERIALSINFORMATION

www.ti.com

4-Mar-2011

TAPEANDREELINFORMATION

*Alldimensionsarenominal

Device

PackagePackagePinsTypeDrawingSOICTSSOPSOICTSSOPSOICTSSOPSOICTSSOP

DPWDPWDPWDPW

1616161616161616

SPQ

ReelReelA0DiameterWidth(mm)(mm)W1(mm)330.0330.0330.0330.0330.0330.0330.0330.0

16.412.416.412.416.412.416.412.4

6.56.96.56.96.56.96.56.9

B0(mm)10.35.610.35.610.35.610.35.6

K0(mm)2.11.62.11.62.11.62.11.6

P1(mm)8.08.08.08.08.08.08.08.0

WPin1(mm)Quadrant16.012.016.012.016.012.016.012.0

Q1Q1Q1Q1Q1Q1Q1Q1

UCC21DRUCC21PWRUCC22DRUCC22PWRUCC23DRUCC23PWRUCC24DRUCC24PWR

25002000250020002500200025002000

PackMaterials-Page1

PACKAGEMATERIALSINFORMATION

www.ti.com

4-Mar-2011

*Alldimensionsarenominal

DeviceUCC21DRUCC21PWRUCC22DRUCC22PWRUCC23DRUCC23PWRUCC24DRUCC24PWR

PackageType

SOICTSSOPSOICTSSOPSOICTSSOPSOICTSSOP

PackageDrawing

DPWDPWDPWDPW

Pins1616161616161616

SPQ25002000250020002500200025002000

Length(mm)

333.2346.0333.2346.0333.2346.0333.2346.0

Width(mm)345.9346.0345.9346.0345.9346.0345.9346.0

Height(mm)

28.629.028.629.028.629.028.629.0

PackMaterials-Page2

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